A processing unit includes, for example, a processing unit core, a primary cache memory, and a secondary cache memory. The secondary cache memory has a larger data storage capacity than the primary cache memory, and therefore has longer readout time. The readout time of the secondary cache memory may cause a reduction in a clock signal frequency.
Related technologies are disclosed in Japanese Laid-open Patent Publication No. 9-116413, Japanese Laid-open Patent Publication No. 2001-166987, and Japanese Laid-open Patent Publication No. 10-312409.